The present invention relates to technique of transmitting a signal between elements such as a CPU and a memory device or memory IC (for example, between digital circuits each composed of CMOS elements or functional blocks of CMOS elements), and, more particularly to techniques of quickly transmitting a signal through one bus in which one main transmission line has plural elements connected thereto.
As a technique of quickly transmitting a signal between digital circuits each composed of a semiconductor integrated circuit, there has been proposed a technique of a low-amplitude interface for propagating a signal having a signal amplitude as low as about 1 volt.
As a representative example of such a low-amplitude interface, a GTL (Gunning Transceiver Logic) interface or a CTT (Center Tapped Termination) interface has been heretofore proposed. These low-amplitude interfaces are discussed in detail in pp 269 to 290 of Nikkei Electronics, Nov. 27, 1993.
FIG. 1 shows a prior art arrangement of such a low-amplitude interface in which one main transmission line has plural branched lines.
A numeral 100 denotes a transmission line terminated by termination power supplies 60 and 61 and termination resistors 50 and 51. The transmission line 100 is connected to a driving circuit block 1 and receiving circuit blocks 2, 3 and 4.
The transmission line 100 has an impedance of 50.OMEGA.. Each of branched lines 11 to 14 has an impedance of 50.OMEGA.. Each of the terminating resistors 50 and 51 has an impedance of 50.OMEGA.. Each voltage of the terminating power supplies 60 and 61 is 0.5 volt. The sending or driving circuit 21 has an on resistance of 10.OMEGA..
When the driving circuit 21 is at a logical "High" output, the circuit 21 operates to connect the transmission line 11 to a 1-volt power supply (not shown). When the driving circuit 21 is at a logical "Low" output, the circuit 21 operates to connect the transmission line 11 to the ground, that is, a 0-volt power supply (not shown). Numerals 32 to 34 denote receiving circuits included in a receiving circuit block, respectively. These receiving circuits compare received signals with the reference voltage V.sub.ref to determine if the received signal is a Low or High level. In this arrangement, V.sub.ref is set at 0.5 V.
Next, a description will be given as to how a signal is transmitted to each point in FIG. 1 on this bus when the driving circuit 21 is switched from the Low output to the High output. At first, a potential of the transmission bus 100 is derived when the driving circuit 21 is at the Low output. The voltage at the point A on the transmission line at this time corresponds to a voltage given by dividing the terminating power source of 0.5 volt by the terminating resistances 50 and 51 and the on resistance of the sending circuit 21. That is, the voltage is derived by: EQU 0.5 V.times.10.OMEGA./(10.OMEGA.+50.OMEGA./2)=0.14 (V)
Next, the potential will be derived of the transmission line which occurs when the output of the sending circuit 21 is switched from the Low output to the High output so that a signal is transmitted to a point A of FIG. 1 as follows. Immediately after the output of the sending circuit 21 is switched, the power supply voltage is divided by the on-resistance of the sending circuit and the impedance 50.OMEGA. of the transmission line 11. Hence, the potential boost at the point A is derived by: EQU 1 V.times.50.OMEGA./(50.OMEGA.+10.OMEGA.)=0.83 (V)
The addition of the initial voltage 0.14 V and the voltage boost, that is, 0.97 V corresponds to the potential at the point A.
The potential occurring when the waveform of the amplitude of 0.83 V reaches the branch point B is derived as follows. If the transmission line 100 is viewed from the transmission line 11, since the transmission line 100 is divided into two, left and right parts, the virtual impedance of the transmission line 100 if viewed from the transmission line 11 becomes a half of an impedance 50.OMEGA. of the transmission line 100, that is, 25.OMEGA.. On the other hand, since the impedance of the transmission line 11 is 50.OMEGA., the mismatch of the impedance results in bringing about the reflection of a signal at the point B.
The reflective coefficient is derived as follows. EQU (50.OMEGA.-25.OMEGA.)/(50.OMEGA.+25.OMEGA.)=0.33
This means that a one-third part of the signal amplitude of 0.83 V transmitted to the point A, that is, a signal of the amplitude 0.28 V is reflected and returned to the sending circuit side. The signal of the left amplitude 0.55 V is transmitted to the transmission line 100 as a first transmitted wave. Hence, the potential of the transmitted signal corresponds to an addition of 0.55 V and the initial potential, that is, 0.69 V. `
When the signal having the amplitude of 0.28 V returned to the sending circuit reaches the sending circuit, the signal is mirror-reflected and reaches the point B again. A two-third part of the signal passes through the transmission line 100, while the remaining one-third part of the signal is returned to the transmission line 11. According to such an action, the signal travels to and fro on the transmission line 11 again and again. Each time the signal waveform reaches the point B, the two-third part of each waveform is output to the transmission line 100. By this operation, the amplitude of 0.83 V originally at the point A is dividedly transmitted to the transmission line 100 bit by bit.
The signal of 0.69 V which passed through the point B and transmitted to the transmission line 100 reaches the point C. At this point, two transmission lines are each made to have an impedance of 50.OMEGA. before the passage of the signal. Hence, the mismatch of the forward synthesized impedance 25.OMEGA. to the impedance of 50.OMEGA. of the transmission line on which the signal has passed results in bringing about the reflection of the signal.
The reflective coefficient is as follows: EQU (50.OMEGA.-25.OMEGA.)/(50.OMEGA.+25.OMEGA.)=0.33
The potential of the waveform passed through the point C corresponds to a potential derived by multiplying the signal amplitude of 0.55 V at the point B by a transmittance 2/3 (=1-1/3) and adding the initial potential to the multiplied value. That is, EQU 0.55 V.times.2/3+0.14 V=0.50 (V)
A similar reflection takes place at the point E or the point G. The potential at the point E is 0.38 V and the potential at the point G is 0.30 V.
These results are shown in FIGS. 2A to 2C. FIG. 2A shows signals which come to and go out of the point C, that is, a signal of the point B coming to the point C and signals of the point D and the point E going out of the point C. For explaining them clearly, the signal at the point A is shown as well. Likewise, FIG. 2B shows signals which come to and go out of the point E. FIG. 2C shows signals which come to and go out of the point G. In FIGS. 2A to 2C, a numeral 201 denotes a signal waveform at the point A in FIG. 1. A numeral 202 denotes a waveform at the point B. A numeral 203 denotes a waveform at the point C. A numeral 204 denotes a waveform at the point D. A numeral 205 denotes a waveform at the point E. A numeral 206 denotes a waveform at the point F. A numeral 207 denotes a waveform at the point G. A numeral 208 denotes a waveform at the point H. When the signal drops, the same thing takes place. The signal waveforms at the drop of the signal are as shown in FIGS. 3A to 3C. In FIG. 3, numerals 201 to 208 denote signal waveforms at the point A to the point H shown in FIG. 1, respectively.
From the situation described above, it is understood that the use of the conventional signal transmitting circuit makes it impossible to allow the first signal at the point A indicating a High level from the driving circuit 21 to exceed the reference voltage Vref (0.5 V in the above condition) at all of the receiving circuit blocks for establishing that the signal is at the High level. In other words, due to the large degree of reflection at the various points B, C, E and G, the original High level voltage at the point A for the first signal is attenuated to very low levels of voltage that will not exceed the reference voltage V.sub.ref at the receivers. Therefore, even though the sending circuit 21 is indicating a High level, the receivers 32, 33 and 34 will not be able to recognize this for the first signal. Eventually, after repeated signals, the level of voltage at points B, C and D will increase to levels much closer to the level at point A, but, until this occurs, the receivers will not be able to recognize the High level.
The signal entering each branched line at the branch point C, E or G, like the transmission line 11, is reflected over and over inside of the branched line. When the reflected waveform returns to the branch point, the two-third part of the signal goes to the transmission line 100. This brings about a waveform distortion on the transmission line 100.
As mentioned above, in the foregoing prior art, the reflections take place at each branch point. The potential drops resulting from the reflections are overlapped with each other. Hence, the rise of the signal potential is delayed in a remote place of the driving circuit. This results in disadvantageously increasing the delay time, and thereby prevents quickly transmitting the signal.
Further, the signal entered into the receiving circuit block is reflected in the receiving circuit part and then goes into the transmission line 100. This also results in disadvantageously distorting the signal waveform, thereby lowering the reliability of the signal transmission.
To speed up the signal transmission and make the signal amplitude on the line 100 smaller, the above prior art is arranged so that the supply voltage is 1 V. In the circuit discussed in the aforementioned paper, to achieve an amplitude of 1 V at the normally used power supply of 3.3 V, the driving circuit is arranged to give a special value of 100.OMEGA. to its on-resistance for realizing a small amplitude.
The special value given to the on resistance as mentioned in the paper, however, makes the widely available transistors having an on resistance of about 10 W useless. In other words, specially designed transistors are required.
Further, such a higher on resistance given to the sending circuit 21 leads to increasing the power consumption of the driving circuit, thereby disadvantageously increasing the overall power consumption.
As another known prior art arrangement relevant to the present invention, U.S. Pat. No. 4,922,449 to Donaldson et al may be referred to. This U.S. Patent discloses a technique of providing a resistor between a circuit block and an inter-block signal transmission line in a circuit line structure having plural circuit blocks containing a driving circuit and a receiving circuit and the inter-block signal transmission line for propagating a signal between the circuit blocks. The object of providing the resistor therebetween is for reducing passage current appearing at the time of signal collision by the source switching operation, that is, reducing the amplitude of the signal on the inter-block signal transmission bus. The resistance is set as 20 W to 40 W. This resistance may bring about a signal reflection at a branch point between the transmission line inside of the circuit block and the inter-block transmission line. The signal reflection may disadvantageously inhibit the realization of fast signal transmission. That is, this technique does not define any resistance based on a relation of an impedance between the inter-block signal transmission line and the signal transmission line inside of the block.
Moreover, another prior art arrangement which provides a resistor between an inter-block signal transmission line and a signal transmission line inside of the circuit block is disclosed in JP-B-54-5929. In this prior art arrangement, a resistor is provided only between the circuit block on the side of the receiving circuit and the inter-block signal transmission line, but no resistor is provided between the circuit block provided with a sending circuit and the inter-block signal transmission bus. Like U.S. Pat. No. 4,922,449, a signal reflection takes place when the signal outputted from the sending circuit is transmitted onto the inter-block signal transmission bus. As in the previously described arrangement, this signal reflection may disadvantageously inhibit realization of fast signal transmission.